In the integrated circuit (IC) industry, devices fabricated in parallel on a large substrate, such as a 300 mm or 450 mm wafer, are typically sorted based on an electrical test (E-test) at the back end of line (BEOL). The devices are singulated into chips following a backside wafer grind. Singulated die identified good at the BEOL E-test are then assembled into a package. A final functional test of the packaged die is then performed. As post-singulation die processing and package assembly practices become more complex, it becomes more important to perform one or more E-test on unpackaged die, for example to filter out die that passed BEOL E-test but have since become unsuitable for packaging.
E-testing of unpackaged die is a significant challenge because of the small dimensions, and vast number of testable points (e.g. top-level metallization) on modern ICs. For example, a microprocessor die may have thousands of testable points. E-testing of a packaged die is comparatively easy as the package assembly breaks out the top-level die metallization (e.g., having a pitch of 100 μm, or less) to packaged electrical connections of much larger dimensions. To perform a comprehensive E-test on an unpackaged die, a prober of an electrical testing apparatus (E-tester) may be coupled to a die through a space transforming prober interface.
During testing, the space transformer must withstand repetitive interfacing with consecutive unpackaged die under test (DUT). Top-level interconnect geometries (e.g., having a pitch of 100 μm, or less) must be accommodated as they are scaled, so electrical probe pin dimensions and alignment are critical to ensure accurate testing without damage to the DUT. Furthermore, many testing algorithms place the DUT under thermal stress, for example testing at temperatures of 200° C., or more. Therefore the space transformer must also be robust to such thermal cycling.
Space transformer architecture is therefore important for high E-tester up-time.